1. Field of the Invention
The present invention relates to a non-volatile semiconductor device and to a method of making a non-volatile semiconductor device. The invention provides a reduced program disturbance caused by a punch-through that may occur while programming a selected cell. The invention also ensures an adequate amount of on-cell current thereby facilitating an appropriate and accurate on/off sensing decision.
2. Description of the Related Art
Non-volatile semiconductor devices having a flash memory cell are able to delete and/or store data electronically, and are capable of storing data even without power. These devices therefore are attaining a wide-spread applicability in a variety of technical fields. Among these devices, the NOR-type non-volatile semiconductor device, which is generally related to the present invention, typically is structured to have a plurality of memory cell transistors connected in parallel to a bit line. The NOR-type devices usually have only one transistor connected between a drain and a source, which also are connected to the bit line. This configuration increases the memory cell current and enables a high speed operation.
Because the memory cell is connected to the bit line in parallel, the cells adjacent to a common bit line are over-deleted, or inadvertently deleted, when reading the selected cell. In addition, if the threshold voltage (Vth) of the memory cell transistor becomes lower (for example, 0V) than the voltage applied to the control gate of a non-selected cell, a malfunction (read-disturbance) occurs. The malfunction occurs because current flows regardless of whether the selected cell is in the on or off (on/off) position, and thus, all of the cells are read as on-cells.
In an effort to solve this problem, a memory cell of a non-volatile semiconductor device has been fabricated so that an additional transistor, (for example, a transistor of the selected gate), is further provided between a drain and a source so that the two transistors form one memory cell (i.e., a flash memory cell). Flash memory cells having two transistors in one memory cell, however, are too large, which is in direct contrast to the current trend of minimizing the chip size. Accordingly, these semiconductor devices are not widely utilized.
To solve this problem, the art recently has provided non-volatile semiconductor devices having various structures, including those known as xe2x80x9csplit gate type semiconductor devices.xe2x80x9d In these devices, a word line (i.e., the selected gate and the control gate) typically is formed on an upper part of a floating gate having electrons, and on both sidewalls of the device.
FIG. 1 is a section view illustrating the structure of a flash memory cell of a non-volatile semiconductor device manufactured by SST (Silicon Storage Technology Co. Ltd.). FIG. 2 is a circuit view illustrating the structure of the entire cell array of this memory cell.
With reference to FIG. 1, a conventional flash memory cell of a split gate type semiconductor device can be described structurally as follows. A floating gate 14, usually made from a polysilicon material, is formed on a predetermined part of a semiconductor substrate 10 having a gate insulating layer 12 disposed thereon. An isolation insulating layer 16 is formed on top of the floating gate 14, and a tunneling insulating layer 18 that is used for deleting data is formed on the substrate 10, which includes the isolation insulating layer 16. The tunneling insulating layer 18 also is formed on both sides of the floating gate 14.
A word line 20, usually made from a polysilicide or polycide material, then is formed on a predetermined part of the insulating layers 16 and 18. The word line 20 serves as a selected gate and a control gate. Channel regions (not shown) under the floating gate 14 and the word line 20 are connected in parallel between the source 22 and the drain 24. Thus, the memory cell is formed to operate as a selected gate transistor I and a memory gate transistor II. In this configuration, the memory cell transistor is at a high, low or negative Vth state depending upon the amount of electrons present in the floating gate 14.
Accordingly, the non-volatile semiconductor device having the thus-structured flash memory cell performs a series of operations related to storing, deleting, and reading data as follows. A program related to storing data is performed in a hot electron injection (HEI) or Fowler-Nordheim (F-N) tunnel method. Erasing, which is related to deleting data, is performed in a F-N method. The following exemplifies a case where the program is performed in a HEI method.
First, a program related to storing data will be described. If a high voltage (for example, xe2x89xa112V) is applied to a source 22 of the memory cell at a state where Vss (0V) is applied to a drain 24 through the bit line, the floating gate 14 is arranged to have a predetermined voltage due to a coupling by the voltage. If a predetermined voltage (for example, Vth) is applied to the word line 20, a channel is formed between the source 22 and the drain 24, and electrons generated in the drain 24 are injected into the floating gate 14 by the HEI method. As a result, a program is made so that data are written in the erased cell. If the voltage applied to the word line 20 is controlled appropriately, the electric field is magnified around the edge of the floating gate 14 so that the programming effect is increased and the current between the source 22 and drain 24 is decreased, thus reducing the power consumption. If the floating gate 14 is filled with electrons, however, the electrons increase the Vth level in the memory cell. Thus, if the cell is read with a reference voltage (Vrefxe2x89xa13 to 4V), which can be applied to the control gate of the word line 20, a channel is not formed because Vth is too high. As a consequence, current cannot flow, and only one state is memorized.
Second, a program related to erasing data and data deletion will be described. If a high voltage (for example, 15V) is applied to the word line 20 of the memory cell at a state when Vss (0V) is applied to the drain 24 and the source 22 through the bit line, electrons stored in the floating gate 14 pass through the tunnel insulating layer 18 in the F-N tunnel method. Electrons flow because of the electric field between the word line 20 and the floating gate 14, and the electrons flow off to the word line 20. As a consequence, data deletion is performed.
If the Vth level of the cell is decreased because there are no electrons in the floating gate 14, and if a reference voltage (Vrefxe2x89xa13 to 4V) is applied to the control gate of the word line 20 to thereby read the cell, a channel is formed in the cell because of the low Vth. Because the channel is formed, current flows and thus, the device memorizes another state which is different from the first state. Thus, data reading is performed by deciding if there is current in the transistor of the memory cell. The decision is made by applying a predetermined voltage to the bit line and word line 20 of the selected cell.
Table 1 is provided to more fully understand the conditions for the operating voltage typically required for programming, erasing, and reading operations.
If the flash memory cell of the non-volatile semiconductor device is structured as in FIG. 1, however, program disturbance can occur when a high voltage is applied during the programming operation. This disturbance can occur because the source (S/Ln) is held in common with the selected cell A1, and because 0V is applied to the word line (W/Ln) of the non-selected cell A2 adjacent to the selected cell A1 on the same bit line (B/Ln).
In addition, if there is a defect in the tunnel insulating layer 18, a reverse tunneling disturb is generated causing a malfunction where the non-selected cell (erased cell) A2 is re-programmed. Meanwhile, a malfunction occurs if the selected gate of the word line gets shorter because of a misalignment, or if Vth of the memory cell is decreased because of defects in the method of making the device, each of which can cause a xe2x80x9cpunch-through phenomenon.xe2x80x9d The malfunction occurs where the non-selected cell (erased cell) A2 is programmed because of the punch-through disturbance.
To prevent this malfunction caused by the punch-through phenomenon, a conventional technique has been provided where the insulating layer under the selected gate of word line 20 is made thicker, which in turn increases the Vth of the selected gate. In this technique, however, because the insulating layer typically is used for the tunneling insulating layer or for the gate insulating layer of a high voltage transistor, there is a limit in how much the thickness of the layer can be increased. Accordingly, it is difficult to apply this technique to the actual process of making the semiconductor device.
A more recent technique to improve the program disturbance of the flash memory cell is to implant boron impurities under the selected gate that comprises the floating gate 14 and the word line 20 when fabricating a memory cell. Implanting the boron impurities prevents the punch-through phenomenon that occurs between the drain 24 and the source 22 when high voltage is applied to the source 22 or, as shown in FIG. 2, two word lines (W/Ln(odd), W/Ln(even)) form one page and divide the horizontal source line. Despite the advantages realized from implanting these boron impurity ions, problems arise when high voltage is applied to source 22 because, when driving the device, it is difficult to make an appropriate and accurate on/off sensing decision. The decision is difficult because the on-cell current of the non-selected cell A2 is decreased. Other problems arise when two word lines form one page because integration of the cell is decreased due to a source being formed in every page. A solution to these problems is urgently needed.
Accordingly, the present invention is directed to a non-volatile semiconductor device and to a method of making such a device that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
A feature of the present invention therefore is to provide a non-volatile semiconductor device and a method of making such a device where the device contains an anti-punch through region surrounding the drain region of the memory cell formation part, and surrounding the source and drain regions of the low voltage transistor formation part. Such a device can reduce and/or prevent a program disturbance due to a punch-through caused in programming of a selected cell, and can ensure a predetermined amount of on-cell current thereby facilitating an appropriate and accurate on/off sensing decision. An additional feature of the present invention is to fabricate the non-volatile semiconductor device more effectively.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The features and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other features of the present invention, as embodied and broadly described, there is provided a non-volatile semiconductor device including:
a substrate;
a memory cell formation part disposed on a predetermined part of the substrate, the memory cell formation part having at least a drain region;
a peripheral circuit part disposed on a predetermined part of the substrate, the peripheral circuit part having a high-voltage transistor formation part and a low-voltage transistor formation part, wherein each high-voltage transistor formation part and low-voltage transistor formation part includes at least a source and a drain region; and
an anti-punch through region surrounding: (a) the drain region in the memory cell formation part; and (b) the drain and source region of the low-voltage transistor formation part.
In accordance with an additional feature of the invention, there is provided a method of making a non-volatile semiconductor device including:
providing an insulating substrate comprising a memory cell formation part and a peripheral circuit part having a high-voltage transistor formation part and a low-voltage transistor formation part;
successively forming a semiconductor layer and a random layer on the insulating substrate;
etching a predetermined portion of the random layer to expose a predetermined portion of the surface of the semiconductor layer in the memory cell formation part;
selectively implanting impurity ions into the exposed surface of the semiconductor layer to thereby form a conductor in a specific part of the semiconductor layer;
forming an isolation insulating layer having edges on the memory cell formation part using the etched random layer as a mask;
removing the etched random layer;
forming a floating gate having at least two sidewalls by etching the semiconductor layer by using the isolation insulating layer as a mask;
forming an insulating layer having a predetermined thickness on the substrate including the edges of the isolation insulating layer and the sidewalls of the floating gate to form an insulating layer surface;
forming a conductive layer on the insulating layer surface;
selectively etching a predetermined part of the conductive layer to form: (a) a word line having sidewalls in the memory cell formation part; and (b) a gate having edges in the high and low-voltage transistor formation parts in the peripheral circuit part;
selectively implanting first conductivity type impurity ions into the memory cell formation part of the substrate where the word line is not formed and overlapping a predetermined portion of the floating gate, thereby forming a source region in the memory cell formation part of the substrate;
selectively implanting first conductivity type impurity ions into the high-voltage transistor formation part in the peripheral circuit part thereby forming a first lightly doped drain (LDD) region in the substrate on the edges of the gate in the high-voltage transistor formation part;
selectively implanting first conductivity type impurity ions into the low-voltage transistor formation part, and into the memory cell formation part to thereby form: (a) a second LDD region in the substrate overlapping with a predetermined portion of the word line; and (b) a third LDD region in the substrate on the edges of the gate in the low-voltage transistor formation part;
tilt-implanting second conductivity type impurity ions into the low-voltage transistor formation part, and into the memory cell formation part to thereby form an anti-punch through region surrounding the second and third LDD regions in the substrate;
forming a spacer on: (a) the sidewalls of the word line; (b) one sidewall of the floating gate; and (c) the edges of the gate in the high and low-voltage transistor formation parts; and
implanting first conductivity type impurity ions into the substrate thus forming a drain region in the memory cell formation part, and source and drain regions in each of the high and low-voltage transistor formation parts.
The thus-structured non-volatile semiconductor device of the present invention improves the punch-through characteristic of the non-selected cell by using the anti-punch through region. The device of the invention provides these improved characteristics even when the channel becomes short or Vth is decreased due to defects in the method of making the device. Thus, when programming the selected cell, the invention prevents the programming of a non-selected cell by the punch-through phenomenon. In addition, when reading the selected cell, the invention ensures a predetermined amount of on-cell current suitable for making an appropriate and accurate on/off sensing decision.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.